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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The MC54/74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 264 FETs or 66 Equivalent Gates MC54/74HC273A J SUFFIX CERAMIC PACKAGE CASE 732-03 1 20 20 1 N SUFFIX PLASTIC PACKAGE CASE 738-03 DW SUFFIX SOIC PACKAGE CASE 751D-04 DT SUFFIX TSSOP PACKAGE CASE 948E-02 20 1 20 1 ORDERING INFORMATION LOGIC DIAGRAM 3 4 7 8 13 14 17 18 19 11 2 5 6 9 12 15 16 MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXADT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS Ceramic Plastic SOIC TSSOP D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK PIN ASSIGNMENT RESET Q0 D0 D1 Q1 Q2 D2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CLOCK RESET 1 PIN 20 = VCC PIN 10 = GND D3 Q3 GND 10/95 (c) Motorola, Inc. 1995 IIIIIIIIIIIIIII II III I I IIIIIIIIIIIIIII I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II III I II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII IIIIIIIIIIIII I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII IIIIIIIIIIIII I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II Design Criteria Value 66 Units ea ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product 1.5 5.0 W pJ .0075 * Equivalent to a two-input NAND gate. 3-1 REV 6 FUNCTION TABLE Inputs Reset L H H H H Clock X D X H L X X Output Q L H L No Change No Change L IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* MOTOROLA DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) RECOMMENDED OPERATING CONDITIONS MC54/74HC273A Symbol Vin, Vout Symbol Symbol VCC Vout Tstg ICC Iout VCC Vin PD TL VOH tr, tf Iin TA VIH VIL Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package (Ceramic DIP) Storage Temperature Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package DC Supply Current, VCC and GND Pins DC Output Current, per Pin DC Input Current, per Pin DC Output Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Input Rise and Fall Time (Figure 1) Operating Temperature, All Package Types DC Input Voltage, Output Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Parameter Parameter Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Vin = VIH or VIL |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v v v v VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Test Conditions - 0.5 to VCC + 0.5 - 1.5 to VCC + 1.5 3-2 - 65 to + 150 - 0.5 to + 7.0 - 55 Min 2.0 Value 0 0 0 0 50 25 20 260 300 750 500 450 + 125 1000 500 400 VCC Max 6.0 VCC V 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Unit Unit mW mA mA mA _C _C _C ns V V V V V - 55 to 25_C 0.5 1.35 1.8 1.5 3.15 4.2 3.98 5.48 1.9 4.4 5.9 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Guaranteed Limit v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 0.5 1.35 1.8 1.5 3.15 4.2 3.84 5.34 1.9 4.4 5.9 v 0.5 1.35 1.8 1.5 3.15 4.2 3.7 5.2 1.9 4.4 5.9 v Unit V V V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIII I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol Symbol VOL tPHL tPLH tPHL tTLH tTHL fmax CPD ICC Cin Iin Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Maximum Low-Level Output Voltage Power Dissipation Capacitance (Per Enabled Output)* Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Propagation Delay, Reset to Q (Figures 2 and 4) Maximum Propagation Delay, Clock to Q (Figures 1 and 4) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Parameter Parameter Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Vin = VCC or GND Iout = 0 A Vin = VCC or GND * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v v Test Conditions 3-3 VCC V VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 6.0 6.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C - 55 to 25_C Typical @ 25C, VCC = 5.0 V 0.1 0.26 0.26 145 29 25 145 29 25 6.0 30 35 4.0 0.1 0.1 0.1 10 75 15 13 Guaranteed Limit Guaranteed Limit 1.0 0.33 0.33 180 36 31 180 36 31 5.0 24 28 0.1 0.1 0.1 10 95 19 16 40 48 1.0 220 44 38 220 44 38 160 110 22 19 4.0 20 24 0.4 0.4 0.1 0.1 0.1 10 v 85_C v 125_C v 85_C v 125_C MC54/74HC273A MOTOROLA MHz Unit Unit A A pF pF ns ns ns V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIII I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIII I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIII I I I I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIII I I I I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIII I I I I I I I I II I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) MOTOROLA MC54/74HC273A Symbol tr, tf trec tsu tw tw th Maximum Input Rise and Fall Times Minimum Pulse Width, Reset Minimum Pulse Width, Clock Minimum Recovery Time, Reset Inactive to Clock Minimum Hold Time, Clock to Data Minimum Setup Time, Data to Clock Parameter Fig. 1 2 1 2 3 3 3-4 VCC Volts 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C Min 5.0 5.0 5.0 3.0 3.0 3.0 60 12 10 60 12 10 60 12 10 1000 500 400 Max Min 5.0 5.0 5.0 3.0 3.0 3.0 75 15 13 75 15 13 75 15 13 Guaranteed Limit v 85_C 1000 500 400 Max High-Speed CMOS Logic Data DL129 -- Rev 6 Min 5.0 5.0 5.0 3.0 3.0 3.0 90 18 15 90 18 15 90 18 15 v 125_C 1000 500 400 Max Unit ns ns ns ns ns ns MC54/74HC273A SWITCHING WAVEFORMS tr CLOCK 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL tPHL trec VCC CLOCK 50% GND tf VCC GND RESET 50% GND tPHL Q 50% tw VCC Figure 1. Figure 2. VALID VCC DATA 50% GND tsu CLOCK th VCC 50% GND EXPANDED LOGIC DIAGRAM Figure 3. D0 3 C DR C D1 4 DR C Q 2 Q0 Q 5 Q1 TEST POINT OUTPUT DEVICE UNDER TEST DATA INPUTS D2 7 DR C Q 6 Q2 D3 8 DR C Q 9 Q3 NONINVERTING OUTPUTS CL* D4 13 DR C Q 12 Q4 * Includes all probe and jig capacitance D5 14 DR C Q 15 Q5 Figure 4. Test Circuit D6 17 DR C DR Q 16 Q6 D7 18 Q 19 Q7 11 1 High-Speed CMOS Logic Data DL129 -- Rev 6 3-5 MOTOROLA MC54/74HC273A OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 732-03 ISSUE E B A F C L DIM A B C D F G H J K L M N NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 20 1 11 10 N H D SEATING PLANE G K J M -A- 20 11 N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E B 1 10 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 -T- SEATING PLANE K M E G F D 20 PL N J 0.25 (0.010) M 20 PL 0.25 (0.010) TA M M TB M DIM A B C D E F G J K L M N -A- 20 11 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E 10X -B- 1 10 P 0.010 (0.25) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 20X D M 0.010 (0.25) TA S B J S F R X 45 _ C -T- 18X SEATING PLANE G K M MOTOROLA 3-6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC273A OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A 20X K REF M 0.15 (0.006) T U S 0.10 (0.004) TU S V S K K1 2X L/2 20 11 B L PIN 1 IDENT 1 10 J J1 -U- SECTION N-N N 0.15 (0.006) T U S 0.25 (0.010) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ A -V- N F C D 0.100 (0.004) -T- SEATING PLANE G H DETAIL E Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 High-Speed CMOS Logic Data DL129 -- Rev 6 CODELINE 3-7 *MC54/74HC273A/D* IIII IIII IIII IIII IIII M DETAIL E -W- DIM A B C D F G H J J1 K K1 L M MC54/74HC273A/D MOTOROLA |
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